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    Home»Tools»NeoLogic raises $10 million to push its CMOS+ technology that cuts die size, improves yield, and addresses rising wafer costs
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    NeoLogic raises $10 million to push its CMOS+ technology that cuts die size, improves yield, and addresses rising wafer costs

    onlyplanz_80y6mtBy onlyplanz_80y6mtAugust 27, 2025No Comments3 Mins Read
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    NeoLogic raises $10 million to advance CMOS+ CPUs, decreasing circuit complexityCMOS+ permits 6-32 enter gates, decreasing energy use and die sizeFirst processors anticipated in 2026, concentrating on power environment friendly AI information middle workloadsNeoLogic has raised $10 million in in Sequence A funding as it really works to alter how processors are designed.Based in 2021, the Israel-based firm (with a US presence deliberate for the longer term) shouldn’t be specializing in transistor scaling, the normal path of the semiconductor business, however fairly on decreasing the complexity of circuits.Its CMOS+ know-how integrates normal CMOS gates with diminished complexity gates, reducing transistor counts by as a lot as thrice at any course of node.

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    As much as 50% decrease power useConventional CMOS is restricted by fan-in, with gates sometimes dealing with not more than 4 inputs.Designers depend on tree constructions to deal with increased inputs, which will increase each chip space and energy use.NeoLogic’s CMOS+ permits single stage gates that deal with between 6 and 32 inputs, shortening the vital path whereas decreasing space and power consumption.The corporate says processors constructed with CMOS+ can decrease energy use by as much as 50 p.c and scale back chip space by as much as 40 p.c whereas retaining latency on par with present designs.Signal as much as the TechRadar Professional publication to get all the highest information, opinion, options and steering your enterprise must succeed!These enhancements are suitable with present CMOS manufacturing processes, from 130nm all the way down to 2nm, in addition to normal EDA instruments, so adoption received’t require new infrastructure.By reducing die dimension and enhancing yield, CMOS+ offers price benefits at superior nodes, the place wafer prices and improvement bills rise sharply.It’s extra than simply gates, nevertheless, as CMOS+ additionally affords energy environment friendly registers, buffers, and arithmetic blocks. Collectively, NeoLogic says, these parts give chip designers a brand new infrastructure that simplifies processor design whereas attaining higher energy and space tradeoffs.“We’re backing NeoLogic as they push the boundaries of computing with their breakthrough strategy to energy-efficient processors,” stated Talia Rafaeli, Companion at KOMPAS VC, which led the most recent funding spherical. “The crew’s deep technical experience and progressive CMOS+ know-how place them to impression the AI information middle area considerably.”NeoLogic sees CMOS+ as a strategy to ship extra environment friendly computing with out departing from established instruments and processes. It has begun demonstrating its first processors to prospects and expects deployment in information facilities beginning in 2026.Through eeNews EmbeddedYou may also like

    Addresses CMOs costs cuts die improves million NeoLogic Push raises rising size technology wafer yield
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